Digilent Idea Space

Have an idea for a product, feature, or improvement? This is the place where you can share those ideas with Digilent’s product team as well as view and vote on Ideas submitted by other Digilent users.

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    Welcome and guidelines

    Welcome to the Digilent Idea Space! If you have an idea for a product feature or improvement the floor is yours! Some guidelines: This space is purely for Ideas about new product features or improvements. Not support. The best place to find support is on our forums (https://forum.digilent.com/) and our reference library (https://digilent.com/reference/) Keep us lean There is a chance you aren't the first one to have your idea. Before submitting an idea, make sure to do a quick search. If you find an idea that is similar to your own, upvote it and leave a comment with any additional thoughts you think should be included in the idea. Add topic tags to your idea These help keep everything organized and easy to find. Some ideas span multiple topic tags. You can add multiple! If you don't have something nice to say....well you know.. Be kind :)

    Britt Espinosa

    0

  2. Decoder for ARM ETMv3, ITM, and TPIU to logic/protocol

    Adding a decoder for ARM ETMv3, ITM, and TPIU trace protocols to Diligent Waveforms would be huge. Most mainstream Arm based MCUs allow for use and configuration of the Embedded Trace Macrocell/Buffer. This allows for advanced debugging far beyond that available through SWD. Trace in debugging is not widely used, due, in my opinion, to the price of the tools which can decode these signals. The most popular debug utilities which support this are the Arm ULINKPro, and the SEGGER J-Trace series, which are thousands of dollars. Having this feature added to Waveforms would add both a competitive edge not seen in competing products and allow students and hobbyists to access a feature of Arm CPUs only available to professionals with enterprise budgets. This decoder has already been added to the opensource PulseView program and can be accessed using an extremely inexpensive FX2 based logic analyzer. To see the blog explaining the process, see this link https://essentialscrap.com/tips/arm_trace/.

    Brian C
    #Software#Improvement#Waveforms

    0

  3. A template/generator for AXI4-Lite IPs that takes register specifications as input

    Xilinx's AXI IP template is known to have some bugs (https://zipcpu.com/blog/2021/05/22/vhdlaxil.html) and can be cumbersome for users who are brand new to using Zynq devices. A well-tested and protocol-compliant template that would allow users to create an IP directly from a description of the functionality they actually care about - the registers that connect to the logic they are trying to control - would significantly speed up this process. Similar open-source projects exist (https://github.com/rggen/rggen for example), however, the easiness of their integration into Vivado is questionable. Taking inspiration from rggen, an IP generator could be implemented in TCL which composes a AXI4-lite design including the desired functionality, described in a custom JSON format, which creates a fully packaged AXI IP including stub drivers to be brought up into Vitis/SDK through a BSP.

    Arthur B
    #FPGA#Improvement

    14

  4. ZYNQ SOM

    Many times I need some features of a development board that I can not find in the market boards. In this cases, SOM are very useful because I can develop my own board without the difficult of routing an FPGA or a DDR Memory. The idea is to create a board like CMOD but using a a Zynq.

    Pablo T
    #New Product#Hardware#FPGA

    2

  5. AI circuit detector/importer

    This feature will allow users to upload an image of a circuit, where an AI will detect the components used and their connections, which will then be imported into the Multisim Live circuit editor. This will remove the need of manually placing components in order to recreate another circuit.

    Nita E
    #Software#New Feature#Multisim Live

    1

  6. Cmod A7 with more I/O

    (Idea submitted to the Digilent forums, 07/27/2022) I like the CModA7 but wish it had a few more I/Os; I am always running out. A 64-pin dip module would be great.

    Britt Espinosa
    #New Product#Hardware#Accessories

    2

  7. Ethernet Development Board

    Since the trend is to more and more Ethernet based systems, a Board with a prety large SoC device would be interesting and at least 4 Ethernet boards would be great

    Sven M
    #New Product

    1

  8. Add the protocol alalyzer function for RS232, 485, 422

    I would like to thank you for Your Good product, specially Analog Discovery and Digital Discovery. I like to suggest the function of the protocol alalyzer for RS232, 485, 422 in Analog Discovery. UART(3.3V, or 5V) protocol analyzer is convenient on Board level debugging. But in System level debugging, RS232, rs422 voltage level are monitored. Your product of Analog Discovery has analog input feature over RS232, rs485 Already. These days I try to buy the RS232 option of oscilloscope by Tektronix. The price is over $3000 in Korea. if your product has that function, the engineers in the world have much better time with their family. Maybe your benifit also become much better.

    Anonymous Wrasse
    #New Feature

    0

  9. Add saved presets

    Allows the user to save a component with custom settings, like saving the J/K flip-flop as the 74LS76N by saving it with the "Negative_Edge_Trigg_CLOCK" and "ACTIVE_LOW_SET_and_RESET" enabled, allowing the user to place it down using the preset.

    Anonymous Penguin
    #New Feature#Improvement#Multisim Live

    1

  10. Zmod 10G Ethernet PHY

    Slow Pmod's won't handle the bandwidth needs for 10G, but Zmod (Syzygy) should.

    Bradford M
    #New Product#Hardware#Accessories

    0

  11. GNU Octave support

    Create a plugin to support Digilent devices with GNU Octave.

    Britt Espinosa
    #Software#New Product#Hardware

    1

  12. Bring back the NetFPGA-1G-CML

    A board with 4 Gigabit Ethernet Ports, can be used for many applications for IIOT or Industry 4.0.

    Sven M

    0

  13. Software-controlled sample rates on the Eclypse Z7

    Default sample rates in projects for the Eclypse Z7 usually test the limits of the Zmod hardware, using >40 MS/s sample rates. While this is useful for many users who want to look at small fast signals, other users who have lower-frequency signals of interest either need to work with buffers that are much larger than they actually wish to, or are potentially completely unable to capture said signal (in the case that buffers are too large fit in memory). Depending on the implementation, this may also allow the Eclypse to be used as a data logging device, capturing on the order of a point per second. A user posted on the Digiilent Forum wanting to vary the sample rate on the fly, in order to create equal-length buffers at different time scales: https://forum.digilent.com/topic/23725-memory-management-eclypse-z7/ This could be accomplished in a couple of different ways: Controlling clocking wizard IP via an AXI interface in order to reduce the sample rate - potentially requires modifications to front-end IP. Decimation/averaging of input streams in PL with ratios modifiable through AXI configuration IP.

    Arthur B
    #New Feature#FPGA#DAQ and Data Logging

    0

  14. Run Petalinux and standalone operating systems on different Zynq CPU cores of the same board at the same time

    A baremetal project could be run in one Zynq CPU which would provide a standard software interface to a Petalinux instance running on the other CPU. This would allow software development to be more easily split into two layers, one which can service PL hardware and hardware drivers in real-time, while the other could implement complex software and leverage premade libraries and drivers for things like data transport between the embedded device and the cloud or a host PC. Additionally, the separation of Petalinux development and baremetal project development would allow multiple developers to work in tandem, and allow the baremetal side to be tested on its own without the need for a complete solution. Such a project could target any number of boards, but a DMA-heavy system like a project for Eclypse or the Zybo Z7 would be ideal. The Petalinux layer could be used to export data (like captured video frames or signal acquisitions) to a host. Xilinx XAPP 1078 claims to implement such a system: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841668/Multi-OS+Support+AMP+Hypervisor https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841653/XAPP1078+Latest+Information

    Arthur B
    #New Feature#FPGA#Improvement

    0

  15. It would be nice to have the ability to imoprt SPICE models

    The current database is extensive, however its missing numerous components. Since its SPICE base simulation, maybe unlocking the ability to import custom models might not be a bad idea.

    Anonymous Pelican
    #New Feature#Hardware#Multisim Live

    0