Digilent Idea Space

Xilinx's AXI IP template is known to have some bugs (https://zipcpu.com/blog/2021/05/22/vhdlaxil.html) and can be cumbersome for users who are brand new to using Zynq devices. A well-tested and protocol-compliant template that would allow users to create an IP directly from a description of the functionality they actually care about - the registers that connect to the logic they are trying to control - would significantly speed up this process. Similar open-source projects exist (https://github.com/rggen/rggen for example), however, the easiness of their integration into Vivado is questionable. Taking inspiration from rggen, an IP generator could be implemented in TCL which composes a AXI4-lite design including the desired functionality, described in a custom JSON format, which creates a fully packaged AXI IP including stub drivers to be brought up into Vitis/SDK through a BSP.

Need better sample rate than 3000 series, but I run on macOS and ubuntu on arm. I particularly like the linux mode of the 3000 series as well as its range of capabilities. I will never consider buying an instrument requiring anything with windows. Also it would be great to use a more modern usb connector i.e. usb c or thunderbolt and get higher data transfer rates. Seems like your higher end instrument has not caught up yet.

Many times I need some features of a development board that I can not find in the market boards. In this cases, SOM are very useful because I can develop my own board without the difficult of routing an FPGA or a DDR Memory. The idea is to create a board like CMOD but using a a Zynq.

(Idea submitted to the Digilent forums, 07/27/2022) I like the CModA7 but wish it had a few more I/Os; I am always running out. A 64-pin dip module would be great.

Since the trend is to more and more Ethernet based systems, a Board with a prety large SoC device would be interesting and at least 4 Ethernet boards would be great

Slow Pmod's won't handle the bandwidth needs for 10G, but Zmod (Syzygy) should.

Create a plugin to support Digilent devices with GNU Octave.

A board with 4 Gigabit Ethernet Ports, can be used for many applications for IIOT or Industry 4.0.

Default sample rates in projects for the Eclypse Z7 usually test the limits of the Zmod hardware, using >40 MS/s sample rates. While this is useful for many users who want to look at small fast signals, other users who have lower-frequency signals of interest either need to work with buffers that are much larger than they actually wish to, or are potentially completely unable to capture said signal (in the case that buffers are too large fit in memory). Depending on the implementation, this may also allow the Eclypse to be used as a data logging device, capturing on the order of a point per second. A user posted on the Digiilent Forum wanting to vary the sample rate on the fly, in order to create equal-length buffers at different time scales: https://forum.digilent.com/topic/23725-memory-management-eclypse-z7/ This could be accomplished in a couple of different ways: Controlling clocking wizard IP via an AXI interface in order to reduce the sample rate - potentially requires modifications to front-end IP. Decimation/averaging of input streams in PL with ratios modifiable through AXI configuration IP.

A baremetal project could be run in one Zynq CPU which would provide a standard software interface to a Petalinux instance running on the other CPU. This would allow software development to be more easily split into two layers, one which can service PL hardware and hardware drivers in real-time, while the other could implement complex software and leverage premade libraries and drivers for things like data transport between the embedded device and the cloud or a host PC. Additionally, the separation of Petalinux development and baremetal project development would allow multiple developers to work in tandem, and allow the baremetal side to be tested on its own without the need for a complete solution. Such a project could target any number of boards, but a DMA-heavy system like a project for Eclypse or the Zybo Z7 would be ideal. The Petalinux layer could be used to export data (like captured video frames or signal acquisitions) to a host. Xilinx XAPP 1078 claims to implement such a system: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841668/Multi-OS+Support+AMP+Hypervisor https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841653/XAPP1078+Latest+Information

There are many very fine, rare and older classic instruments that use an electrostatic X, Y, Z CRT in vector mode, to display their measurement results. Some of these instruments were made by some of the best companies of their era: HP, Tektronix, etc. Such as the Tek 576 Curve Tracer, or the HP 9100a/b Calculator/ Computer that issued in the era of Personal Computing (ca 1968). The problem is that the electrostatic CRT's are dying, due to mechanical shock of filament burn out. So, the question is: can a LCD module with a DigiLent backbone be used to replace these old CRT's, by tapping into the analog low voltage deflection circuits of these old instruments. We are not talking about the Raster Scan CRT to VGA modules available on eBay for ~ $30 etc. Instead, we are speaking about something a little bit more complex that is inside these old instruments, to help keep them alive for another century for museums, schools and collectors, appreciative of where the engineering designs came from and evolved. For an example, the HP 9100 Calculator was designed with discrete transistors, diodes, etc. for everything including the ALU. Information can be found at the HP Museum: The video circuitry can be found in the hp 9100 Service Manual, & HP 9100b Schematics on the HP museum web site: http://www.hpmuseum.net/search.php Tony Duell has provided hand sketched schematics http://www.hpmuseum.net/document.php?hwfile=989 HP Docs: 9100b Flowchart 21 pages: https://archive.org/details/bitsavers_hp91009100_26784192 9100b Schematics 12 pages: https://archive.org/details/bitsavers_hp91009100_28364269 Just a thought !

How about a RISC-V based version of a Zynq, not with the Zynq's hard-coded CPU but as a reference design in an off the shelf fpga. A CMod would work, preferably with more I/O pins. This is something I'm working towards myself, but something from Digilent would enable many developers and makers. Use an FPGA that leaves room for adding ports, modules, accelerators etc.

Syzygy supports 25Gbps presumably per differential pair (and there are 8 of them) so this shouldn't be a problem for Thunderbolt-4 or upcoming Thunderbolt 5. This would vastly improve ability to interface Zmod-capable baseboards with external peripherals, displays, or other computer systems.

Zmod should have plenty of bandwidth to support one or more SATA-III connections. Most mid priced FPGA baseboards don't include SATA (some Opal Kelly do), so this would be a welcome addition.